This application is based upon and claims priority of Japanese Patent Application No. 2002-207254, filed on Jul. 16, 2002, the contents being incorporated herein by reference.
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device including a step of dry etching a silicon nitride film selectively, and more particularly to a method of manufacturing a semiconductor device suitable for manufacturing a flash memory.
2. Description of the Prior Art
Referring to FIGS. 1 to 6, a conventional method of manufacturing a NOR-type flash memory will be first described.
FIGS. 1A to 1C are plan views showing, in the order of steps, an example of the conventional method of manufacturing a flash memory; and FIGS. 2 to 6 are cross-sectional views similarly showing the method of manufacturing a flash memory in the order of steps. Note that FIGS. 1A to 1C are plan views of a memory cell formation portion. Moreover, note that FIGS. 2A, 3A, 4A, 5A and 6A illustrate cross-sections of a peripheral circuit formation portion and that FIGS. 2B, 3B, 4B, 5B and 6B illustrate cross-sections taken along the line Ixe2x80x94I in FIG. 1A. Moreover, in order to simplify the description, a transverse direction of FIG. 1A will be referred to as an X direction and a longitudinal direction thereof will be referred to as a Y direction.
First, as shown in FIG. 1A, a plurality of trenches arrayed in the X and Y directions are formed on a semiconductor substrate 50. Then, an insulator is buried in the trenches, thus forming an element isolation film 51. Thereafter, as shown in FIGS. 2A and 2B, a silicon oxide film 52 is formed by subjecting a surface of the semiconductor substrate 50 to thermal oxidation.
Next, a conductive polysilicon film 53 is formed on an entire upper surface of the semiconductor substrate 50. Then, the conductive polysilicon film 53 in the memory cell formation portion is patterned, thus forming a plurality of strip-shaped polysilicon films 53 extending in the Y direction as shown in FIG. 1A. These strip-shaped polysilicon films 53 are formed so as to have both side edge portions thereof in their width direction overlap with edge portions of two element isolation films 51 adjacent to each other, respectively.
Next, an intermediate insulating film 54 is formed over the entire upper surface of the semiconductor substrate 50. Thereafter, a photoresist film 57 is formed on this intermediate insulating film 54, and an opening portion is provided in the resist film 57 by executing an exposure/developing process thereto. Accordingly, as shown in FIG. 2A, the intermediate insulating film 54 in the peripheral circuit formation portion is exposed.
Thereafter, by use of the resist film 57 as a mask, the intermediate insulating film 54 and the polysilicon film 53 in the peripheral circuit formation portion are sequentially etched and removed. After completing the etching, the resist film 57 is removed.
After removing the intermediate insulating film 54 and the polysilicon film 53 in the peripheral circuit formation portion as described above, as shown in FIGS. 3A and 3B, a conductive polysilicon film 58 is formed over the entire upper surface of the semiconductor substrate 50, and a silicon oxide film 59 and a silicon nitride film 60 are further formed thereon. Thereafter, on the silicon nitride film 60, a resist film 61 is formed in a predetermined shape. Then, the silicon nitride film 60, silicon oxide film 59, polysilicon films 58 and 58a, intermediate insulating film 54 and polysilicon film 53 are sequentially etched by use of the resist film 61 as a mask. After completing the etching, the resist film 61 is removed.
By this etching, as shown in FIGS. 4A and 4B, a gate electrode 58b made of polysilicon is formed in the peripheral circuit formation portion, and a floating gate 53a and a control gate 58a, which are made of polysilicon, are formed in the memory cell formation portion. As shown in FIG. 1B, the control gate 58a extends in the X direction, and one floating gate 53a is formed for each memory cell.
Next, by use of the silicon nitride film 60 in the memory cell formation portion as a mask, ion implantation of impurities is performed to the surface of the semiconductor substrate 50 via the silicon oxide film 52. Thus, a source layer 62s and a drain layer 62d are formed. As shown in FIG. 1B, the source layer 62s is formed to extend in the X direction, and the drain layer 62d is formed in a region surrounded by the element isolation films 51 and control gates 58a. 
Moreover, by use of the silicon nitride film 60 in the peripheral circuit formation portion as a mask, ion implantation of impurities is performed to the surface of the semiconductor substrate 50 via the silicon oxide film 52. As a result, lightly doped drain (LDD) layers 62b are formed on both sides of a gate electrode 58b, respectively.
Thereafter, the silicon nitride film 60 is removed by wet etching using thermal phosphoric acid.
Next, a silicon oxide film is formed over the entire upper surface of the semiconductor substrate 50, and anisotropic etching is carried out thereto. Thus, as shown in FIGS. 5A and 5B, sidewalls 63a are formed respectively on both sides of each floating gate 53a and each control gate 58a in the memory cell formation portion, and sidewalls 63b are formed respectively on both sides of the gate electrode 58b in the peripheral circuit formation portion. Thereafter, by use of the gate electrode 58b and the sidewalls 63b as a mask, ion implantation of impurities at a high density is executed to the substrate surface in the peripheral circuit formation portion. Thus, on both sides of the gate electrode 58b, source/drain layers 64b are formed, respectively.
Next, a metal film is formed over the entire upper surface of the semiconductor substrate 50, and heat treatment is given thereto. Thus, metal atoms in the metal film and silicon atoms of the control gate 58a, gate electrode 58b and source/drain layer 64b are reacted to each other. Accordingly, as shown in FIGS. 6A and 6B, silicide films 65a, 65b and 65c are formed. Thereafter, the non-reacted metal film is removed by etching.
As shown in FIG. 1C, a silicon oxide film is next formed as an interlayer insulating film 66 over the entire upper surface of the semiconductor substrate 50. Then, by photolithography, contact holes 66h are formed, respectively, which reach to the silicide film 65c and the source layer 62s from an upper surface of the interlayer insulating film 66. After that, a metal film is formed over the entire upper surface of the semiconductor substrate 50, and this metal film is patterned. Thus, bit lines 67a extending in the Y direction are formed in the memory cell formation portion, and wirings 67b are formed in the peripheral circuit formation portion. The bit lines 67a are electrically connected to the drain layers 62d in the memory cell formation portion through the contact holes 66h, and the wirings 67b are electrically connected to the source/drain layers 64b in the peripheral circuit formation portion through the contact holes 66h and the silicide films 65c. In such a manner, a flash memory is completed.
However, the inventor of the present application considers that there are problems described below in the conventional semiconductor device manufacturing method described above.
Normally, in order to prevent a leak of an electric charge from the floating gate 53a to the control gate 58a, the intermediate insulating film 54 has, as shown in FIG. 7, a three-layered structure of a first silicon oxide layer 54a, a silicon nitride layer 54b and a second silicon oxide layer 54c. 
In the conventional semiconductor device manufacturing method, when the silicon nitride film 60 is removed by wet etching using thermal phosphoric acid, the silicon nitride layer 54b of the intermediate insulating film 54 is inevitably etched (side-etched) in a horizontal direction (see FIG. 7). For this reason, in forming an interlayer insulating film, a hollow space occurs between the floating gate 53a and the control gate 58a, and a parasitic transistor is generated in this space. This parasitic transistor causes changes in a write voltage and a read voltage of a memory cell, and thus reliability of a semiconductor device is lowered.
In order to prevent the side-etching of the silicon nitride layer 54b, dry etching is conceivable instead of the wet etching using thermal phosphoric acid. For example, in Domestic Re-publication of PCT Publication WO98/16950, described is a method of selectively etching a silicon nitride film by setting a mixture ratio of CH2F2 gas to O2 gas in the range of 0.2 to 0.6.
Moreover, in Japanese Patent Laid-Open No. Hei 8(1996)-59215, described is a method of selectively etching a silicon nitride film by using a mixed gas of O2 gas and either of CH3F gas and CH2F2 gas.
However, by use of these dry etching methods, a ratio of an etching rate of the silicon nitride to an etching rate of the silicon oxide (an etching selectivity) is about 4 to 6, which is relatively small. For this reason, when such methods are applied to the above-described step of removing the silicon nitride film 60, the silicon oxide film 52 covering over a lightly doped drain layer 62b in the peripheral circuit formation portion is etched to be reduced in thickness in removing the silicon nitride film 60. Thus, in an extreme case of the above, the surface of the semiconductor substrate 50 is exposed. Accordingly, contamination such as carbon or a carbon compound, which is contained in an etching gas, is introduced into the lightly doped drain layer 62b. As a result, in the silicide film formation step, portions where the silicide film is not formed (circled portions in FIG. 8) occur as shown in FIG. 8, thus resulting in a contact failure.
Moreover, in the conventional method, when the silicon nitride film 60 is removed by etching, the element isolation film 51 is also etched to generate a concave portion as shown in FIG. 9A, thereby increasing an aspect ratio (a/b) between the control gates 58a. Therefore, as shown in FIG. 9B, in forming the interlayer insulating film 66, an insulator is not completely buried in the concave portion between the control gates 58a, thus generating a hollow space (a so-called xe2x80x9cporexe2x80x9d) 69. As a result, a write voltage and a read voltage of a memory cell are changed, and thus reliability of a semiconductor device is lowered.
In consideration of the above, an object of the present invention is to provide a method of manufacturing a semiconductor device in which an etching rate of a silicon nitride is increased compared to an etching rate of a silicon oxide.
The method of manufacturing a semiconductor device is the one including the steps of forming a silicon oxide film and a silicon nitride film above a semiconductor substrate and of dry etching the silicon nitride film, wherein the silicon nitride film is etched by using CH3F gas, CH2F2 gas or a mixed gas thereof and O2 gas as an etching gas, by setting a pressure inside a reaction chamber in the range of 10.6 to 13.3 Pa (80 to 100 mTorr), and by setting a flow rate of the O2 gas to be five times that of the CH3F gas, CH2F2 gas or mixed gas thereof or more.
Therefore, an etching selectivity of the silicon nitride film with respect to the silicon oxide film increases as much as 15 or more, thus enabling the silicon nitride film to be etched while hardly etching the silicon oxide film.